Blocks (what I build and ship)
This page highlights projects that represent what I want to be known for: digital chip design, verification, and practical use of GenAI in engineering workflows.
Each item is written as an artifact: what it is, what I owned, and what evidence exists.
Each item is written as an artifact: what it is, what I owned, and what evidence exists.
Featured
SaxoFlow — Open-source design + verification suite (AI-assisted)
SaxoFlow reduces setup friction and repetitive work by combining open-source EDA tools with GenAI-assisted workflows.
What exists today
- Interactive CLI to install and manage open-source EDA tools
- Agents supporting RTL, testbench-based verification, and formal verification
- Copilot-style navigation for flows and debugging
What I’m building next
- Retrieval-grounded help (RAG) over docs/specs/project context
- Lightweight IDE experience so students can use the flow without living in the terminal
Read case study →
Floating-point formal verification — RTL-to-RTL model checking
A scalable verification approach for floating-point arithmetic using direct RTL-to-RTL model checking against a golden reference, supported by staged helper assertions and refinement.
Read case study →
RISC-V Processor “Kreacher” — RTL design + SoC integration
A collaborative RISC-V processor integrated into a SoC environment, with emphasis on correctness and integration readiness.
My contributions
- Implemented datapath modules including the ALU and decoder
- Focused on functional accuracy and clean integration
Read case study →
Additional technical projects
Neural Processing Unit blocks — BatchNorm + Softmax processing elements
Designed configurable processing elements and supporting control/memory components for Batch Normalization and Softmax.
What I built
- Configurable compute blocks, memory + control units, and integration logic
- Post-implementation functional simulation and timing simulation
Outcome
- Exceeded state-of-the-art benchmarks in performance and resource utilization in Vivado (details available on request)
Physical design optimization — Carry-save array multiplier
Optimized the physical design of a carry-save array multiplier with a practical PPA focus.
Outcome
- Reduced area by ~60% and improved performance by ~4× through floorplanning and placement strategy changes
Related topics
Want to see the evidence trail end-to-end?
If you’re hiring for verification, building proof-oriented flows, or evaluating GenAI-assisted verification automation, reach out. I can share additional artifacts that are safe to discuss.